1. Field of the Invention
The invention relates to memory. More particularly, the invention relates to configuring a mirror sense amplifier in order to create a reference current by which to read the state of flash memory cells.
2. The State of the Art
A system for reading flash memory typically employs a differential sense amplifier to compare the amount of current flowing through a reference cell to a selected memory cell. A sensing circuit determines if the selected memory cell has logic 1 or logic 0 stored therein based on the comparison.
When the amount of current flowing through the reference cell is larger than the amount of current flowing through the selected memory cell then logic value 0 (programmed) is read from the memory cell. When the amount of current flowing through the reference cell is smaller than the amount of current flowing through the selected memory cell then logic value 1 (erased) is read from the memory cell.
A current reference, generally half the current of an erased cell (logic value 1), enables the system to determine, through comparison with the current of the memory cell, what logic value is stored in the selected memory cell. The current reference is typically set so that the system distinguishes between programmed and erased states.
A reference cell generates the reference current. The reference cell is located in an array outside the memory array in order to avoid the write and erase cycles that modify the threshold of the reference cells. The reference current is carried around the chip by a system of current mirrors.
FIG. 1 illustrates system 10 wherein local mirror 12 mirrors a reference current inside sense amplifier 15.
Sense amplifier 15 has bias circuit 17 to bias a bit line. Reference voltage generator 19 provides a voltage level, usually generated from the reference cell current, for comparator 21. Comparator 21 determines if the reading array cell is erased or programmed.
Memory access time depends on how rapidly the reference current circuit can turn on. Node 16 is precharged at a reference value and allowed to evolve. Equalization circuitry (not shown) permits the evolution of charge at node 16. The equalization circuitry produces a load effect on a signal on line 18.
One drawback to the aforementioned design is that since the signal on line 18 is the same for all sense amplifiers 15, the load effect may reduce the performance for fast memory access. Additionally, the added load effect of the equalization circuitry increases memory access time. Furthermore, frequent reading of the memory cells may change the threshold voltages of the reference cells and therefore compromise their reliability.
The minimum Vcc for circuit 20 used to bias the reference cell depends on p-channel transistor 11 in diode configuration and on cascode 13 that biases the reference bit line at about 1V, so that if transistor 11 is conductive enough then its VGS can be approximated to its threshold VthP1 and minimum Vcc isVCC=VTHP1+1V+VDSATN1. In modern, low voltage circuits the minimum Vcc should be as low as possible.